Automatic latency balancing in VHDL-implemented complex pipelined systems

Balancing (equalization) of latency in parallel paths in the pipelined data processing system is an important problem. Without that the data from different paths arrive at the processing blocks in different time cycles, and incorrect results are produced. Manual correction of latencies is a tedious and error-prone work. This paper presents an automatic method of latency equalization in systems described in VHDL. The method is based on simulation and is portable between different simulation and synthesis tools. The method does not increase complexity of the synthesized design comparing to the solution based on manual latency adjustment. The example implementation of the proposed methodology together with simple design demonstrating its used is available as an open source project under BSD license. keywords: FPGA, latency, balancing, delay, equalization, VHDL, Python